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Company

Cadence

Cadence Design Systems is a major electronic design automation (EDA) vendor providing software and IP for chip, circuit, and system design.

Known aliases

  • Cadence Design Systems
  • Uber Cadence

Current stories

buildOne report1 publisher

NVIDIA's cuPotential claims a further 2-3x on atomic simulation that already runs on GPUs

NVIDIA says its new cuPotential library speeds up already GPU-optimized atomic simulation by a further 2-3x in early-access testing. The 30x figures in the same release belong to other libraries.

Reality

Evidence25
Adoption15
Hype gap+20
Incentives80
Confidence55
buildConfirmed3 publishers

Rapidus signs 17 design partners while its 2nm foundry still looks for customers

Rapidus has signed 17 partners, including Synopsys and Infosys, to help customers design chips for its 2nm foundry, backed by $15bn of state money. It still has to win the customers who will fill that fab before production starts in the second half of next fiscal year.

Perspective Coverage

3 publishers
Builder
Builder 30%
Operator
Operator 30%
Investor
Investor 40%

Reality

Evidence60
Adoption12
Hype gap+20
Incentives65
Confidence58
buildConfirmed3 publishers

Vinci raises $250M to take its chip thermal simulator into vibration and electromagnetics

Vinci raised $250 million at a $1.5 billion valuation to extend its chip thermal simulator into vibration and electromagnetics. Its self-reported speed now has to hold up in repeated production use, next to the Cadence and Synopsys tools already in design flows.

Perspective Coverage

3 publishers
Builder
Builder 37%
Operator
Operator 22%
Investor
Investor 41%

Reality

Evidence55
Adoption18
Hype gap+40
Incentives65
Confidence60
buildOne report1 publisher

Amazon's $1bn-plus Synopsys deal tunes chip-design simulation for Trainium and Graviton

Amazon will license Synopsys IP and expand its use of Synopsys chip-design tools in a multi-year deal reported at over $1 billion. Synopsys's pledge to tune its simulation software for Trainium and Graviton does more for AWS's position than the license does.

Publishers:tomshardware.com

Reality

Evidence45
Adoption20
Hype gap+20
Incentives75
Confidence45
buildOne report1 publisher

OpenAI's hardware head calls Jalapeno's nine months from RTL to tapeout the new baseline

OpenAI took its Jalapeno chip from RTL to tapeout in nine months with its own AI models, against a norm its hardware head puts at 18 to 24 months. The count stops at first tapeout, before a B0 stepping reported to be up to 25% more efficient per watt.

Publishers:tomshardware.com

Reality

Evidence35
Adoption20
Hype gap+35
Incentives65
Confidence40
buildOne report1 publisher

Synopsys sets end-2026 general availability for its AgentEngineer chip-design agents

Synopsys plans general availability at the end of 2026 for AgentEngineer, chip-design agents covering six domains on a new Autopilot Platform. Chip teams now have a named product and a date to plan around, though the speed claims still have to be proven on their own flows.

Publishers:tomshardware.com

Reality

Evidence45
Adoption25
Hype gap+40
Incentives70
Confidence55
buildOne report1 publisher

Cognichip's one detailed ACI example divides out to 40 to 50 times faster

Faraj Aalaei's Cognichip argues that semiconductor physics belongs inside the model, with agents left to orchestrate. The one speedup it has documented in detail is a 55-page spec handled in days against a baseline Cognichip supplied itself.

Publishers:runtimewire.com

Reality

Evidence33
Adoption18
Hype gap+42
Incentives74
Confidence57
buildOne report1 publisher

Temporal's $550M round values durable execution at 2.5x its February price

Lightspeed co-led a $550 million Series E on September 14th, seven months after Temporal's $5 billion Series D. The operating metrics behind the markup are Temporal's own: 4,300 paying customers and 1.9 trillion billable actions in August.

Publishers:runtimewire.com

Reality

Evidence45
Adoption62
Hype gap+22
Incentives78
Confidence52
investOne report1 publisher

JEDEC's LPDDR6 supports flexible 32-byte minimum access granularity for AI workloads

The published spec quantifies pins, rails and access sizes but never a data rate, which tells you the decisions device makers face for the next several years are about granularity and board cost rather than headline bandwidth.

Publishers:jedec.org

Reality

Evidence63
Adoption22
Hype gap+31
Incentives84
Confidence57
buildOne report1 publisher

Temporal talks $12B six months after $5B: durable execution is now agent infrastructure

A reported $500 million round at a pre-money floor of at least $12 billion reprices a two-decade systems bet. Teams already running workflows on it should treat this as a procurement event.

Publishers:runtimewire.com

Reality

Evidence55
Adoption66
Hype gap+27
Incentives70
Confidence54
buildOne report1 publisher

The optical interconnect bill: $144B by 2030, and 63.7% of it is silicon photonics

A forecast filed with a Hong Kong IPO puts data center optics at $144.4 billion in 2030, and the $15 billion already spent means rack decisions made now are bets on a moving roadmap.

Publishers:tomshardware.com

Reality

Evidence34
Adoption32
Hype gap+38
Incentives82
Confidence45